The present invention relates to VLSI circuit fabrication and more particularly to forming conductive interconnects between vertically spaced conductive levels. In VLSI circuit fabrication, it is important to form stepless interconnects between various levels, and for the interconnect metal to have a highly planar top surface upon which the second level metal layer can be uniformly deposited and thereafter patterned by fine line photolithography.
The prior art technique for forming such interconnects has been to form a via or aperture in the dielectric layer which separates the conductive levels, and then to fill or plug the via with a conductive material. A widely used process is to form aluminum plugs in the via by a lift-off process following deposition of a thin barrier layer of titanium-tungsten within the via upon the semiconductive substrate. The barrier layer prevents the diffusion of aluminum and spiking into the semiconductive substrate, which is typically silicon. Another barrier layer material is platinum silicide, which can be covered with titanium-tungsten defined by a lift-off process. The fabrication of such barrier layers and interconnects which require barrier layers involves extra processing steps.
It has been known that tungsten can be selectively chemically vapor deposited (CVD) for use in VLSI circuit fabrication. Such tungsten deposits exhibit low resistivity, and such processes are described in "Hot-Wall CVD Tungsten for VLSI", by N. Miller and I. Beinglass, Solid State Technology, December 1980, pp. 79-82.